Processors, Parallel Processing and Virtual Machines

Computer Science A2 · Hardware and Virtual Machines. The idea in plain words, the rules to remember, the mistake to avoid and a worked example, written and checked by Mega Lecture.

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The idea

RISC processors have a small set of simple, fixed-length instructions, few addressing modes and many registers. CISC processors have a large set of complex instructions of different lengths, so a program needs fewer instructions but each can take several clock cycles.

Simple, equal instructions make pipelining easy: while one instruction is executed, the next is decoded and a third is fetched. When an interrupt comes, several instructions are part-way through, so the pipeline must be dealt with before the routine runs.

Parallel computers are classed by how many instruction streams and data streams they have: SISD, SIMD, MISD, MIMD. A virtual machine is software that behaves like a separate computer on a host.

Rules to remember

RISC: few instructions, fixed length, few addressing modes, many general-purpose registers, hard-wired control unit, only LOAD and STORE use memory, easy to pipeline.
CISC: many instructions, variable length, many addressing modes, fewer registers, microprogrammed control unit, hard to pipeline.
Pipelined time for n instructions with k stages, no stalls = k + (n − 1) clock cycles; without a pipeline it is k × n.
Interrupt: checked at the end of the fetch–execute cycle; the program counter and registers are saved, the interrupt service routine runs, then the registers are restored.
SISD: one processor, one data stream. SIMD: the same instruction on many data items at once (arrays, graphics). MISD: several processors, different instructions, the same data. MIMD: several processors, different instructions, different data (multi-core).
Massively parallel computer: a very large number of processors linked together, working on parts of one problem and passing messages to each other.
Virtual machine: lets another OS or old software run on a host and be tested safely; it runs more slowly than real hardware and depends on the host.

Common mistake

Students work out pipelined time as stages × instructions. Only the first instruction needs all the stages; after that one instruction finishes every clock cycle, so add 1 cycle for each further instruction.

Worked example

A processor has a four-stage pipeline and each stage takes one clock cycle. There are no stalls or branches. How many clock cycles are needed to complete 12 instructions, and how many are saved compared with no pipelining?

The first instruction finishes after 4 cycles.
Each of the other 11 instructions finishes one cycle later: 4 + 11 = 15 cycles.
Without a pipeline: 4 × 12 = 48 cycles.
Saving: 48 − 15 = 33 cycles.

Answer: 15 clock cycles, which is 33 fewer than without pipelining.

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